Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device including a buried gate, a storage node and a bit line, and a method for manufacturing the same.
A Dynamic Random Access Memory (DRAM) includes a plurality of unit cells, each of which includes a capacitor and a transistor. The capacitor is used to temporarily store data therein. The transistor is used to transmit data between a bit line and a capacitor in correspondence with a control signal (i.e., a word line) using the electric conductivity of a semiconductor device, which changes depending on environment. The transistor has three regions including a gate, a source and a drain, and charges between the source and the drain move in response to a control signal input to the gate. The charges between the source and the drain move through a channel region in accordance with the properties and operation of the semiconductor device.
When a general transistor is formed in a semiconductor substrate, a gate is formed in the semiconductor substrate, and impurities are doped at both sides of the gate to form a source and a drain. In this case, a region between the source and the drain under the gate becomes a channel region of the transistor. A transistor with a horizontal channel region occupies a predetermined area of a semiconductor substrate. Reducing the overall area of a complicated semiconductor memory apparatus is difficult due to the plurality of transistors contained in the semiconductor device.
If the overall area of the semiconductor memory apparatus is reduced, the number of semiconductor memory devices capable of being acquired from each wafer is increased, resulting in increased productivity. A variety of methods have been proposed to reduce the overall area of the semiconductor memory device. A representative method uses a recess gate wherein a recess is formed in a substrate and a gate is formed in the recess such that a channel region is formed along a curved surface of the recess, instead of using a conventional planar gate having a horizontal channel region. With the progress of the above recess gate, another method for burying the entirety of the gate in the recess to form a buried gate has also been proposed.
In the buried gate structure, an isolation gate has been used to form a bit line contact and a storage node contact in the form of a line type. However, when the isolation gate structure is employed, a leakage current in the cell area increases compared to the case where a trench-type device isolation film.
When patterning a bit line contact in the buried gate structure employing a trench-type device isolation film, the contact hole must be patterned as a hole type and a dry etch process must be used for such patterning. If the pattern size implementable in a given process is reduced, a contact hole pattern may not be defined on a mask. In addition, when etching a contact hole in an active region in a subsequent etch process, the active region may not be opened. If the pattern size is increased to prevent the above-mentioned problems, short-circuiting may occur between the contact hole and the storage node.
The storage node contact must be formed by a Self Aligned Contact (SAC) after bit-line formation, and contact resistance unavoidably increases as a contact area between the active region and the contact is reduced.
In order to solve the above-mentioned problems, a damascene bit line process has been proposed, which forms a bit line after forming a storage node contact (SNC).
If a damascene bit line process is used, two contiguous SNCs are formed simultaneously, and then each SNC is separated through a subsequent damascene process. Thereafter, a bit line is formed to bury the inside of the damascene pattern. As a result, the patterning caused by the damascene bit line process can be more easily performed than that of a process for independently forming each SNC. In addition, the damascene bit line process is more advantageous in terms of a self aligned contact (SAC) failure than a process in which the SNC is formed later.
In order to prevent the SAC failure from occurring, the size of a lower part of the damascene bit line must be reduced. However, it is difficult to reduce the size of the lower part of the damascene bit line. In addition, when reducing the size of the lower part of the damascene bit line, the size of an upper part of the damascene bit line may increase such that it is larger than the size of the lower part of the damascene bit line. As a result, the upper part of the storage node contact (SNC) plug is reduced in size, and the area of overlap between the SNC plug and a storage node is also reduced in size, resulting in an increase in contact resistance.